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[source in ebook] SystemC片上系统设计源代码

Description: SystemC片上系统设计的源代码： 书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。 本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。 本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Platform: | Size: 2640896 | Author: c.li | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[VHDL-FPGA-Verilog] DCT_1D

Description: 一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper-One-dimensional DCT transform Verilog source code can be used to optimize the JPEG algorithm reference. Procedures used in the algorithm known as the
Platform: | Size: 54272 | Author: 楚天 | Hits:

[Other] iir_par_code

Description: IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
Platform: | Size: 1024 | Author: 无名 | Hits:

[Other] alu_Verilog

Description: It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
Platform: | Size: 5120 | Author: masth | Hits:

[Program doc] xge_mac_latest.tar

Description: Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. -Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
Platform: | Size: 813056 | Author: Maxim | Hits:

[Other] SamilPalnitkar

Description: Verilog HDL A Guide to Digital Design and Synthesis, Second edition IEEE 1364-2001 compliant by Samir Palnitkar. This book will definitely going to be very useful for the beginners as the contents of it are well explained with proper examples and illustrations. The author starts the language from very scratch to professional level.
Platform: | Size: 1723392 | Author: rksant | Hits:

[RFID] 2

Description: RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol which uses cryptographic hash algorithm is based on a three-way challenge response authentication scheme. In addition, we will show how the three different types of protocol frame formats are formed by extending the ISO/IEC 18000-3 standard[3] for implementing the proposed authentication protocol in RFID system environment. The system has been described in Verilog HDL and also synthesized using Synopsys Design Compiler with Hynix 0.25 µ m standard-cell library. From implementation results, we found that the proposed scheme is well suite to implement robust RFID system against active attacks such as the man-in-the-middle attack.
Platform: | Size: 233472 | Author: fxy | Hits:

[Other] Verilog_HDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: lucer_29a | Hits:

[VHDL-FPGA-Verilog] fpu100_latest.tar

Description: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Platform: | Size: 1981440 | Author: 赵恒 | Hits:

[Embeded-SCM Develop] iverilog-0.9.2

Description: iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
Platform: | Size: 1477632 | Author: fanyuchuan | Hits:

[VHDL-FPGA-Verilog] ofdm

Description: ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Platform: | Size: 2048 | Author: 张维 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[Other] design_through_verilog_IEEE

Description: Book name: Verilog author:ieee edition: 2e Very good book
Platform: | Size: 1847296 | Author: honey | Hits:

[VHDL-FPGA-Verilog] emiraga-ieee754-verilog-b7a63aa

Description: IEEE 754 floating point
Platform: | Size: 17408 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[VHDL-FPGA-Verilog] IEEE-standard-Verilog-HDL1364-2001

Description: verilog 硬件描述语言 golden版-verilog hardware descriptor language golden version
Platform: | Size: 2186240 | Author: willow | Hits:

[VHDL-FPGA-Verilog] verilog-RTLevel-Synthesis

Description: 本章详细的分析了寄存器传输级综合，ieee最新标准-IEEE Standard for Verilog® Register Transfer Level Synthesis
Platform: | Size: 380928 | Author: 王凯 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] IEEE_Verilog_2001

Description: 原版IEEE verilog/VHDL 2001标准。-IEEE verilog/VHDL 2001
Platform: | Size: 2182144 | Author: zmm | Hits:
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